Noise floor reduction in image sensors

ABSTRACT

An image sensor array including a first plurality of unit cells coupled to a first sense amplifier, and a second plurality of unit cells coupled to a second sense amplifier, where the first plurality and the second plurality are substantially electrically isolated from each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional PatentApplication Ser. No. 60/252,915, filed Nov. 27, 2000, and entitled“Noise floor reduction in image sensors,” incorporated herein byreference in its entirety.

FIELD OF THE INVENTION

[0002] The present invention relates to imaging electronics in general,and more particularly to noise floor reduction in CMOS process ActivePixel image sensor systems.

BACKGROUND OF THE INVENTION

[0003] CMOS process Active Pixel Sensor (APS) technology is foreseen asthe next generation technology for image sensors, which will replace thecurrently dominating CCD technology. Among the advantages that APStechnology has over CCD technology are the ability to integrate imagesensor and camera electronics onto a single chip, low power dissipationdue to the inherently lower CMOS process voltage as compared with CCDvoltage, and significantly-lower manufacturing costs.

[0004] Dramatic advance in the CMOS process technology are also expectedto lead to the implementation of imagers with a 5 μm pixel pitch on asubmicron CMOS process, which is approximately equal to the diffractionlimit of the camera lens. This limit offsets one of the major advantagesof CCD technology, namely the high fill factor afforded by a very simplepixel circuit.

[0005] The ability to implement photographic-quality imagers using CCDtechnology is severely limited by the large array dimensions that wouldbe required, having thousands of pixel columns and rows. It is difficultto implement such large arrays using CCD technology due to the CCDCharge Transfer Efficiency (CTE) factor which dictates that imagequality severely deteriorates as the size of the image sensor arrayincreases. It is not commercially feasible to produce 3,000×2,000 pixelCCD arrays as would be required for near photographic quality images dueto the prohibitive manufacturing costs involved.

[0006] Although the transition from CCD-based technology to APS-basedtechnology for commercial image sensors appears inevitable, APStechnology has several limitations that have yet to be overcome. Theability to implement large CMOS-based APS image sensor arrays is limitedby readout bus capacitance that originates from multiplexing all pixelswithin each column into a single column line. The parasitic outputcapacitances of the multiplexing circuits and of the line interconnect,normally implemented with metal, are the major contributors to columncapacitance. Thus, for a given CMOS process and pixel unit cell size,the column capacitance is proportional to the number of multiplexedrows.

[0007] The column capacitance is the dominant contributor to theinput-referred noise and it governed by the so-called “kTC” noisemechanism. One technique that may be used to reduce the kTC noise effectinvolves introducing an amplification stage in each pixel's unit cell byincluding an in-pixel Source-Follower circuit. The Source-Followeramplifier “de-couples” the in-pixel integration capacitor from thecolumn capacitance, which results in a reduced input-referred readoutnoise. However, this technique leads to a reduction in gain due to theattenuation of the signal as a function of column bus capacitance. Thiscan be costly in terms of signal-to-noise ratio (SNR) for large-formatcircuits with a high column capacitance and for applications where thecharge that is involved is small. Thus, although implementing aSource-Follower circuit results in a reduced input-referred readoutnoise, its effect diminishes as the imager's size increases due to theincreasing column capacitance.

SUMMARY OF THE INVENTION

[0008] The present intention seeks to provide methods and apparatus fornoise floor reduction in CMOS-based APS image sensor arrays thatovercomes disadvantages of the prior art. The present inventionsubstantially reduces the column capacitance in large image sensorarrays, resulting in a reduced noise floor and a better signal-to-noiseratio. A Direct Injection (DI) circuit approach is employed in place ofthe Source-Follower circuit per unit cell approach. A DI circuit isrelatively simple to implement and deploys less transistors per unitcell, which results in a higher unit cell fill-factor, a smaller pixel,or both. Furthermore, the Fixed Pattern Noise (FPN) of a DI circuit isconsiderably lower than that of the Source-Follower-based unit cell. TheDI circuit of the present invention directly injects the chargeaccumulated by the integration capacitor into the column. This resultsin a significant input-referred readout noise that is higher than thatof the Source-Follower-based unit cell. By reducing column capacitancethe present invention significantly reduces the image sensor's noisefloor and improves its signal-to-noise ratio, particularly in largeimage sensor arrays.

[0009] In one aspect of the present invention an image sensor array isprovided including a first plurality of unit cells coupled to a firstsense amplifier, and a second plurality of unit cells coupled to asecond sense amplifier, where the first plurality and the secondplurality are substantially electrically isolated from each other.

[0010] In another aspect of the present invention each of the first andsecond pluralities of unit cells includes at least one column line.

[0011] In another aspect of the present invention the unit cells arearranged in two or more clusters of two or more of the unit cells each,and the unit cells within each of the clusters are coupled to a clusterline which is coupled to the column line,

[0012] In another aspect of the present invention only one of theclusters is actively connected to the column line at any given time.

[0013] In another aspect of the present invention the unit cells aredirect injection unit cells.

[0014] In another aspect of the present invention the first pluralityand the second plurality are substantially electrically isolated fromeach other by at le 10M Ohms.

[0015] In another aspect of the present invention an image sensor arrayis provided including a plurality of columns, each column including aplurality of unit cells coupled to a column lines a first senseamplifier coupled to a first plurality of the unit cells in each of thecolumns, and a second sense amplifier coupled to a second plurality ofthe unit cells in each of the columns, where the first and secondpluralities of the unit cells in each of the columns are substantiallyelectrically isolated from each other.

[0016] In another aspect of the present invention each of the columnsincludes a plurality of clusters, each cluster including two or more ofthe unit cells coupled to a cluster line which is coupled to the columnline.

[0017] In another aspect of the present invention only one of theclusters is actively connected to the column line at any given time.

[0018] In another aspect of the present invention the unit cells aredirect injection unit cells.

[0019] In another aspect of the present invention the first pluralityand the second plurality are substantially electrically isolated fromeach other by at least 10M Ohms.

[0020] In another aspect of the present invention a method for reducingnoise floor in an image sensor is provided, the method including sensinga first plurality of unit cells with a first sense amplifier, andsensing a second plurality of unit cells with a second sense amplifier.

[0021] In another aspect of the present invention either of the sensingsteps includes sensing different subsets of the unit cells at differenttunes.

[0022] In another aspect of the present invention either of the sensingsteps includes sensing mutually exclusive subsets of the unit cells atdifferent times.

[0023] In another aspect of the present invention each of the sensingsteps includes sensing its associated plurality of unit cells insubstantial electrical isolation from the other the plurality of unitcells.

[0024] In another aspect of the present invention each of the sensingsteps are performed alternatingly.

[0025] The disclosures of all patents, patent applications, and otherpublications mentioned in this specification and of the patents, patentapplications, and other publications cited therein are herebyincorporated by reference in they entirety.

BRIEF DESCRIPTION OF TE DRAWINGS

[0026] The present invention will be understood and appreciated morefully from the following detailed description taken in conjunction withthe appended drawings in which:

[0027]FIGS. 1A and 1B are schematic flow illustrations of a DirectInjection (DI) unit cell 100, useful in understanding the presentinvention;

[0028]FIG. 2 is a schematic illustration of an image sensor arraysegment, useful in understanding the present invention;

[0029]FIGS. 3A and 3B, taken together, are top-view and side-viewillustrations of readout transistor T₂ of FIGS. 1A, 1B, and 2, useful inunderstanding the present invention;

[0030]FIG. 4 is a schematic illustration of an image sensor array,constructed and operative in accordance with a preferred embodiment ofthe present invention; and

[0031]FIG. 5 is a schematic illustration of an alternative image sensorarray column arrangement for use with the image sensor array of FIG. 4,constructed and operative in accordance with a preferred embodiment ofthe present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODLMENTS

[0032] Reference is now made to FIGS. 1A and 1B, which are schematicillustrations of a Direct Injection (DI) unit cell 100, useful inunderstanding he present invention. DI 100 is shown as having aphotodiode PD 102, an integration capacitor C_(mt) 104, a transistor T₁106, column line capacitance C_(col) 108, a readout transistor T₂ 110, acolumn line 112, and transistor gates 114 and 116.

[0033] When an image sensor's background photon noise is low, its noisefloor is determined by the image sensor's electronics, particularly thereadout electronics associated with photocurrent signals, as well as itsinput stages, which in turn determines the image sensor's sensitivity.

[0034] The major noise components which determine the noise floor areFixed Pattern Noise (FPN), 1/f noise, and white noise. A Direct Ejectionstage typically features a very low FPN, and conventional techniques maybe applied to remove 1/f noise. If generated at later stages, whitenoise may also be removed using conventional techniques

[0035] Among the major factors which set the lower bound to noiseoriginating from the pixel readout, the dominant noise component is theso-called kTC noise, which originates from transferring charges fromtheir origin to a collecting capacitor C. The kTC noise originates froma resistor which charges a capacitor. The noise output on the capacitor,<v_(n)>, which originates from a resistor, is expressed: $\begin{matrix}{{\langle v_{n}\rangle} = \sqrt{\frac{kT}{C}}} & \left( {{EQ}.\quad 1} \right)\end{matrix}$

[0036] where k is Boltzmann's constant of 1.38×10⁻²³ Joul/° K., T is theresistor's/capacitor's temperature expressed in degrees Kelvin, C is thecapacitor's capacitance expressed in Farads, and <v_(n)> is thecapacitor's PMS noise voltage expressed in Volts.

[0037] The noise may be expressed in terms of “noise electrons,” that isthe number of electrons that would cause the RMS noise on capacitor C.The RMS number of noise electrons, <N_(n)> may be derived from (EQ. 1)as: $\begin{matrix}{{\langle N_{n}\rangle} = {\frac{1}{e} \cdot \sqrt{kTC}}} & \left( {{EQ}.\quad 2} \right)\end{matrix}$

[0038] where e is the electron charge of 1.6×10⁻¹⁹ Coulomb.

[0039] In FIG. 1A a photon-generated photocurrent I_(ph) flows fromphotodiode PD 102 into integration capacitor C_(int) 104 throughtransistor T₁ 106. The kTC noise source is the transistor T₁ channelresistance. The photocurrent integration stage is depicted in FIG. 1A,and thus the noise source may be defined as the integration noise. Theintegration noise may be expressed in terms of RMS voltage as:$\begin{matrix}{{\langle v_{n}^{int}\rangle} = \sqrt{\frac{kT}{C_{int}}}} & \left( {{EQ}.\quad 3} \right)\end{matrix}$

[0040] where <v_(n) ^(int)> is the RMS integration noise and C_(int) isthe charge integration capacitance. The RMS number of noise electrons<N_(n) ^(int)> may be expressed as: $\begin{matrix}{{\langle N_{n}^{int}\rangle} = {\frac{1}{e} \cdot \sqrt{{kTC}_{int}}}} & \left( {{EQ}.\quad 4} \right)\end{matrix}$

[0041]FIG. 1B shows the path taken by the integrated charge readout fromthe C_(int) to the column line 112. The column line's capacitance isshown as C_(col) 108. The charge transfer is embodied as a current flowthrough a readout transistor T₂ 110. This current flow generates a kTCnoise on the column line, and the noise component is translated into anequivalent noise source on the integration capacitor C_(int). Thisrepresents the noise on the integration capacitor that would result inthe same noise on the column line. This noise is referred to as“input-referred noise,” and is expressed as <v_(n) ^(col)> for the RMSnoise voltage and <N_(n) ^(col)> for the RMS number of noise electrons.It may be shown that $\begin{matrix}{{{\langle v_{n}^{col}\rangle} = {\sqrt{\frac{kT}{C_{int}}} \cdot \left( {\sqrt{\frac{C_{col}}{C_{int}}} + \sqrt{\frac{C_{int}}{C_{col}}}} \right)}}{and}} & \left( {{EQ}.\quad 5} \right) \\{{\langle N_{n}^{col}\rangle} = {\frac{1}{e} \cdot \sqrt{{kTC}_{int}} \cdot \left( {\sqrt{\frac{C_{col}}{C_{int}}} + \sqrt{\frac{C_{int}}{C_{col}}}} \right)}} & \left( {{EQ}.\quad 6} \right)\end{matrix}$

[0042] Typically, C_(col)>>C_(int). Thus, it may be seen that thedominant factor which contributes to noise floor is not the integrationnoise, but rather the noise that originates from the integrated chargereadout to the image sensor's column.

[0043] By way of example, given a 0.6 μm process, a 10 μm×10 μm pixel,and a 1,000-row image sensor, the column capacitance is approximately 4pF, and the integration capacitance is approximately 0.1 pF. In thisexample, the column input-referred readout noise is approximately 6.5times greater than the integration noise. The readout noise isapproximately 40 μV RMS, while the input-referred readout noise isapproximately 1.5 mV. The integration noise is approximately 6 μV rms.

[0044] Thus, it may be seen that the column readout noise is thedominant factor and may be considered to be the noise floor. Significantreduction of the column readout capacitance would therefore result in asignificant noise floor reduction, as the column readout noise isdetermined by the $\frac{C_{col}}{C_{int}}$

[0045] ratio and reduction of C_(col) would result in noise floorreduction.

[0046] Improvement in the signal-to-noise ratio may also be achieved asfollows, Let v_(int) represent the highest possible signal that may becollected on the integration capacitor C_(int) at reaching saturation.Given that column readout noise a dominant contributor to noise floor,the signal-to-noise ratio may be approximated as: $\begin{matrix}{{SNR} \cong \frac{v_{int}}{\langle v_{n}^{col}\rangle}} & \left( {{EQ}.\quad 7} \right)\end{matrix}$

[0047] where SNR is the signal-to-noise ratio at the column line,v_(int) is the near-saturation voltage on the integration capacitance,and <v_(n) ^(col)> is the input-referred column line noise RMS voltage.Thus, for a 5 volt process v_(int) is approximately 1.5 Volts.Continuing with the previous example, given a 373° K. junctiontemperature, the input-referred column readout noise may be as much as˜1.5 mVolts, resulting in a signal-to-noise ratio of approximately1,000. Where column readout noise is negligible, the signal-to-noiseratio is limited mainly by the charge integration noise, beingapproximately 6.5 times better than the signal-to-noise ratio in thisexample.

[0048] Reference is now made to FIG. 2, which is a schematic flowillustration of an image sensor array segment, useful in understandingthe present invention. In FIG. 2 a single column 200 of an X by V-rowsimage sensor array is shown having multiple unit cells 202 connected toa column line 206, where each unit cell includes a Direct Injection (DI)circuit 204 as described hereinabove with reference to FIGS. 1A and 1B.In the configuration shown, when a row is read out, its readouttransistors T₂ conduct a charge, and the charge accumulated on theintegration capacitors of the row is transferred to its respectivecolumn line. All the other readout transistors which reside on eachcolumn are in a cutoff state.

[0049] The column capacitance C_(col) in FIG. 2 may be approximated by:

C _(col) ≅V·(C _(d) +c _(M) ·a)  (EQ. 8)

[0050] where V is the number of image sensor rows, C_(d) is the readouttransistor drain capacitance when in cutoff and when the column isbiased approximately to 0 Volts, c_(M) is the column metal capacitanceper unit length, and a is the pixel pitch for square pixels.C_(col)≅C_(d)+c_(M)·a is thus the column capacitance per pixel, as isshown at reference numeral 208.

[0051] It may thus be seen that column capacitance, which determines thenoise floor, is directly proportional to the number of rows in the imagesensor, and, thus, the larger the image sensor array, the greater thenoise floor.

[0052] Reference is now made to FIGS. 3A and 3B, which are top-view andside-view illustrations of readout transistor T₂ of FIGS. 1A, 1B, and 2,useful in understanding the present invention. In FIGS. 3A and 3B atransistor assembly 300 is shown including a transistor T₂ element 302including a gate 304, a drain 306, a column metal line 308, a fieldoxide element 310, a connection 312 of column metal line 308 to drain306, all overlying a bulk 314.

[0053] In FIGS. 3A and 3B, transistor T₂ is shown with its contact andan adjacent section of column line, typically constructed from M1 metal.It may be seen that the width of transistor T₂ transistor is not minimaldue to the drain-to-column contact rules which require the width oftransistor T₂ to be more than double the minimal possible transistorchannel width. The drain diffusion capacitance and the overlappinggate-drain capacitance determine the drain capacitance C_(d) as follows:

C _(d) ≅C _(gd) +C _(db)  (EQ. 9)

[0054] where C_(gd) is the gate-to-drain overlapping capacitance, andC_(db) is the drain bulk diode capacitance at zero volts. It may furtherbe seen that:

C _(gd) ≅W·L _(OV) ·c _(g)  (EQ. 10)

[0055] where W is the T₂ transistor's width, L_(OV) is the overlappingdistance between the gate and the drain, which is usually derived in anempirical manner, and C_(g) is the gate-bulk capacitance per unit areadetermined by the gate oxide thickness. And finally:

C _(db) ≅c _(jd) ⁰ ·A _(d) +c _(jdsw) ⁰ ·P _(d)  (EQ. 11)

[0056] where c_(jd) ⁰ is the drain junction capacitance at zero voltagebias per area unit, A_(d) is the drain junction area, c_(jdsw) ⁰ is thedrain junction sidewall capacitance per unit length at zero voltagebias, and, P_(d) is the junction periphery length which includes all thejunction sidewalls excluding the gate side.

[0057] By way of example, for a typical 0.6 μm CMOS process, the T₂transistor has

[0058] A_(d)≅2 μm²

[0059] P_(d)≅4 μm

[0060] c_(jd) ^(o)≅0.4 fF/μm²

[0061] c_(jdsw) ^(o)≅0.45 fF/μm

[0062] L_(ov)≅0.1 μm

[0063] Therefore, C_(d) may be expressed as:

C_(d)≅3fF  (EQ. 12)

[0064] The metal capacitance per unit length C_(M) is given by:

c _(M) =c _(M) ^(A) ·W _(M)+2·c _(M) ^(P)  (EQ. 13)

[0065] where c_(M) ^(A) is the metal line capacitance per area unit, andc_(M) ^(P) is the metal capacitance, per line side, per unit length.Thus, for the example 0.6 μm CMOS process, the typical Metal 1capacitances are

c _(M) ^(A)≅0.04 fF/μm ²

c _(M) ^(P)≅0.03 fF/μm

[0066] and a metal width W_(M)≅0.6 μm,

[0067] giving a metal capacitance per unit length C_(M) as

c _(M)≅0.08 fF/μm  (EQ. 14)

[0068] Given EQ. 12 and 14, for a pixel pitch a=10 μm the total columncapacitance per pixel c_(col) may be calculated as:

c _(col)≅3.8 fF/pixel  (EQ. 15)

[0069] Thus if V=1,000, the column capacitance is approximately 3.8 pF.

[0070] The integration capacitor's capacitance value may also becalculated. This value for a 0.6 μm CMOS process is:

C_(int)≅0.1 pF  (EQ. 16)

[0071] Reference is now made to FIG. 4, which is a schematicillustration of an image sensor array 400, constructed and operative inaccordance with a preferred embodiment of the present invention. Thesensor array 400 of FIG. 4 includes one or more columns 402, each havingone or more Direct Injection (DI) unit cells 404 configured as describedhereinabove with reference to FIGS. 1A, 1B, 2, 3A, and 3B. As in mostany two-dimensional array, sensor array 400 may be alternativelyreferred to as having one or more rows of unit cells 404. Each column402 of sensor array 400 is separated into two or more electricallyisolated portions, such as into an upper half 406 and a lower half 408as shown in FIG. 4, thus forming one or more upper half rows and one ormore lower half rows. The separation of the portions of each column issuch that there is little or no conductivity between the portions, suchas a resistance of greater that 10M Ohm. Each electrically isolatedportion is arranged to be read out through a separate sense amplifier,such as is shown in FIG. 4 where each upper half row is arranged to beread out through a top sense amplifier set 410, and each lower half rowis arranged to be read out through a bottom sense amplifier set 412.Sensor array 400 is also preferably configured with a row decoder 414and an output buffer 416.

[0072] Since the upper and lower halves 406 and 408 of each column 402are electrically isolated, the column capacitance which each senseamplifier set faces may be expressed as: $\begin{matrix}{C_{col}^{1} = {\frac{V}{2} \cdot c_{col}}} & \left( {{EQ}.\quad 17} \right)\end{matrix}$

[0073] The associated noise floor is of each sense amplifier set isthus, $\begin{matrix}{{\langle v^{1_{n}}\rangle} = {\sqrt{\frac{kT}{C_{int}}} \cdot \left( {\sqrt{\frac{0.5 \cdot C_{col}}{C_{int}}} + \sqrt{\frac{C_{int}}{0.5 \cdot C_{col}}}} \right)}} & \left( {{EQ}.\quad 18} \right)\end{matrix}$

[0074] where typically C_(col)>>C_(int). The reduction in the noiselevel may then be calculated as: $\begin{matrix}{\frac{\langle v^{1_{n}}\rangle}{\langle V_{n}\rangle} \cong 0.707} & \left( {{EQ}.\quad 19} \right)\end{matrix}$

[0075] Thus, by splitting each column in the array into two halves, thenoise floor is reduced to about 70% of what it would be were the columnsnot split.

[0076] The signal-to-noise ratio of the output data improves by the samefactor as the noise floor reduction as follows: $\begin{matrix}{\frac{{SNR}^{1}}{SNR} \cong \sqrt{2}} & \left( {{EQ}.\quad 20} \right)\end{matrix}$

[0077] where SNR¹ is the signal-to-noise ratio of the split array, andSNR is the signal-to-noise ratio an undivided array as describedhereinabove with reference to FIGS. 1A, 1B, 2, 3A, and 3B. In an arraywhere the columns are split into N portions, the improvement of the SNRwill be on the order of the square root of N.

[0078] Reference is now made to FIG. 5, which is a schematicillustration of an alternative image sensor array column arrangement foruse with the image sensor array of FIG. 4, constructed and operative inaccordance with a preferred embodiment of the present invention. Thesensor array column of FIG. 5, now referred to as column 500, includesone or more Direct Injection (DI) unit cells 502 configured as describedhereinabove with reference to FIGS. 1A, 1B, 2, 3A, and 3B, and isseparated into electrically isolated upper and lower halves as isdescribed hereinabove with reference to FIG. 4. Each half of column 500is segmented into k clusters 504 (shown as 504A, 504B, 504C, and 504D),typically numbering two or more. Each cluster 504 may be expressed as$\frac{V}{k}$

[0079] rows, where V is the number of unit cells 502 in cluster 504, andis interconnected to a column line 506 via a cluster select transistor508 (shown as 508A, 508B, 508C, and 508D) that is controlled by acluster selector 510 (shown as 510A, 510B, 510C, and 510D).

[0080] Typically, during row readout of column 500, only one out of 2·kcluster select transistors 508 in column 500 is “ON”, and all othercluster select transistors 508 in column 500 are “OFF”. The row readouttypically starts with the top cluster 504A, when cluster selecttransistors 508A transistor is “ON”. The first cluster rows are thenselected and sequentially read, starting with row 0, and ending with row$\frac{V}{2 \cdot k} - 1.$

[0081] After all the rows in the top cluster are read out, clusterselect transistor 508A of the top cluster 504A switches from “ON” to“OFF” (i.e., cluster selector 510A goes from “High” to “Low”), andcluster select transistor 508B of the next cluster 504B switches from“OFF” to “ON” ((i.e., cluster selector 510B goes from “Low” to “High”).The rows of cluster 504B are then read sequentially. This operationcontinues until all the rows of the all of the columns 500 of the imagesensor array are read out. As is described hereinabove with reference toFIG. 4, the top half rows of each column 500 is read through a top senseamplifier set, while the bottom half rows of each column 500 is readthrough a bottom sense amplifier set.

[0082] It may be seen that since only one cluster 504 is activelyconnected to column line 506 at a time while all the other clusters arenot actively connected to column line 506, the total parasitic load ofcolumn line 506 is significantly reduced. By way of explanation, assumethat cluster select transistors 508 are of the same dimensions as thereadout transistors T₂ (FIGS. 1A, 1B, 2, 3A, and 3B) in every unit cell.This assumption may be justified, since the transistor's width is muchwider the minimum width, where the width is determined by metal-to-draincontact dimensions and overlap design rules. Thus, putting such twotransistors in series does not significantly slow down the readout.Therefore, the dimensions of cluster select transistor 508 may be giventhe same dimensions as that of readout transistor T₂. This being thecase, the drain capacitance of cluster select transistor 508 isidentical to that of readout transistor T₂. Since k−1 cluster selecttransistors 508 are “OFF” at any given time, their associated clustersare not actively connected to column line 506 and, therefore, do notload the column line.

[0083] The capacitance of column line 506 may be calculated as:$\begin{matrix}{C_{col}^{2} \cong {{\frac{V}{2 \cdot k} \cdot \left( {C_{d} + {c_{M} \cdot a}} \right)} + \left( {{k \cdot C_{d}} + {\frac{V}{2} \cdot c_{M} \cdot a}} \right)}} & \left( {{EQ}.\quad 21} \right)\end{matrix}$

[0084] where$\frac{v}{2 \cdot K} \cdot \left( {C_{d} + {c_{M} \cdot a}} \right)$

[0085] is the capacitance associated with a single currently-readcluster,$\left( {{k \cdot C_{d}} + {\frac{V}{2} \cdot c_{M} \cdot a}} \right)$

[0086] approximates the capacitance associated with the column and thecluster select transistors parasitic capacitance.

[0087] Since it is highly desirable to minimize column capacitance, theoptimal value for k may be found for EQ. 21 as: $\begin{matrix}{k_{opt} \cong \sqrt{0.5 \cdot V \cdot \left( {1 + \frac{c_{M} \cdot a}{C_{d}}} \right)}} & \left( {{EQ}.\quad 22} \right)\end{matrix}$

[0088] Once the optimal number of rows in a cluster is determined, thecolumn capacitance may be also derived from EQ. 21.

[0089] Continuing with the example presented hereinabove, for an imagesensor with 1,000 rows, on a 0.6 μm CMOS process, k_(opt)≅25. Thus, inthis example, each half of the image sensor array should be divided into25 clusters, with 20 rows in each, in order to achieve a minimum columncapacitance of C_(col) ²≅0.55 pF.

[0090] Thus, through column segmentation and image sensor array halving,column capacitance may be reduced approximately by a factor of 7. Thisreduces the noise floor from about 1.5 mVolts to less t 0.7 mVolts inthe present example, and improves the signal-to-noise ratio fromapproximately 1,000, to approximately 2300.

[0091] It is appreciated that several options are available by which thenecessary circuitry described hereinabove may be implemented in aminimum of space. For example, the cluster line may be implemented inM1, while the column line may be implemented over the cluster line inM2. Alternatively, the cluster line may be implemented in Poly, whilethe column line is implemented over the cluster line in M1. The clusterselector lines may also be implemented in Poly. This is feasible sincethe cluster selection is done infrequently, once every$\frac{V}{2 \cdot k}$

[0092] rows. Thus, the longer time it takes to precondition the clusterfor readout is insignificant. It is also possible to alternate thereadout between rows in the upper half of the image sensor array androws in the bottom half. This would effectively double the readout timeper row, and leave significant slack time for cluster switching. If thecluster select line is implemented in Poly, it could be placed over aground line or a signal line which runs in metal, thus reducing spacerequirements even further.

[0093] It is appreciated that one or more of the steps of any of themethods described herein may be omitted or carried out in a differentorder than that shown, without departing from the true spirit and scopeof the invention.

[0094] While the methods and apparatus disclosed herein may or may nothave been described with reference to specific hardware or software, itis appreciated that the methods and apparatus described herein may bereadily implemented in hardware or software using conventionaltechniques.

[0095] While the present invention has been described with reference toone or more specific embodiments, the description is intended to beillustrative of the invention as a whole and is not to be construed aslimiting the invention to the embodiments shown. It is appreciated thatvarious modifications may occur to those skilled in the art that, whilenot specifically shown herein, are nevertheless within the true spiritand scope of the invention.

What is claimed is:
 1. An image sensor array comprising: a firstplurality of unit cells coupled to a first sense amplifier; and a secondplurality of unit cells coupled to a second sense amplifier, whereinsaid first plurality and said second plurality are substantiallyelectrically isolated from each other.
 2. An image sensor arrayaccording to claim 1, wherein: each of said first and second pluralitiesof unit cells comprises at least one column line.
 3. An image sensorarray according to claim 2, wherein: said unit cells am arranged in twoor more clusters of two or more of said unit cells each, and said unitcells within each of said clusters are coupled to a cluster line whichis coupled to said column line.
 4. An image sensor array according toclaim 3 wherein only one of said clusters is actively connected to saidcolumn line at any given time.
 5. An image sensor array according toclaim 1 wherein said unit cells are direct injection unit cells.
 6. Animage sensor array according to claim 1 wherein said first plurality andsaid second plurality are substantially electrically isolated from eachover by at least 10M Ohms.
 7. An image sensor array comprising: aplurality of columns, each column comprising a plurality of unit cellscoupled to a column line; a first sense amplifier coupled to a firstplurality of said unit cells in each of said columns; and a second senseamplifier coupled to a second plurality of said unit cells in each ofsaid columns, wherein said first and second pluralities of of said unitcells in each of said columns are substantially electrically isolatedfrom each other.
 8. An image sensor array according to claim 7 whereineach of said columns comprises a plurality of clusters, each clustercomprising two or more of said unit cells coupled to a cluster linewhich is coupled to said column line.
 9. An image sensor array accordingto claim 7 wherein only one of said clusters is actively connected tosaid column line at any given time.
 10. An image sensor array accordingto claim 7 wherein said unit cells are direct injection unit cells. 11.An image sensor array according to claim 7 wherein said first pluralityand said second plurality are substantially electrically isolated fromeach other by at least 10M Ohms.
 12. A method for reducing noise floorin an image sensor, the method comprising: sensing a first plurality ofunit cells with a first sense amplifier; and sensing a second pluralityof unit cells with a second sense amplifier.
 13. A method according toclaim 12 wherein either of said sensing steps comprises sensingdifferent subsets of said unit cells at different times.
 14. A methodaccording to claim 12 wherein either of said sensing steps comprisessensing mutually exclusive subsets of said unit cells at differenttimes.
 15. A method according to claim 12 wherein each of said sensingsteps comprises sensing its associated plurality of unit cells insubstantial electrical isolation from the other said plurality of unitcells.
 16. A method according to claim 12 wherein each of said sensingsteps are performed alternatingly.
 17. An image sensor array comprising:a first plurality of unit cells coupled to a first sense amplifier; anda second plurality of unit cells coupled to a second sense amplifier,wherein said first plurality and said second plurality are substantiallyelectrically isolated from each other; wherein: each of said first andsecond pluralities of unit cells comprises at least one column line. 18.An image sensor array comprising: a first plurality of unit cellscoupled to a first sense amplifier; and a second plurality of unit cellscoupled to a second sense amplifier, wherein said first plurality andsaid second plurality are substantially electrically isolated from eachother; wherein: said unit cells are arranged in two or more clusters oftwo or more of said unit cells each, and said unit cells within each ofsaid clusters are coupled to a cluster line which is coupled to saidcolumn line.
 19. An image sensor array comprising: a first plurality ofunit cell means coupled to a first sense amplifier; and a secondplurality of unit cell means coupled to a second sense amplifier,wherein said first plurality and said second plurality are substantiallyelectrically isolated from each other.
 20. A method for reducing noisefloor in an image sensor, the method comprising: sensing a firstplurality of unit cells with a first sense amplifier; and sensing asecond plurality of unit cells with a second sense amplifier; whereineach of said sensing steps comprises sensing its associated plurality ofunit cells in substantial electrical isolation from the other saidplurality of unit cells.
 21. A method for reducing noise floor in animage sensor, the method comprising: sensing a first plurality of unitcells with a first sense amplifier; and sensing a second plurality ofunit cells with a second sense amplifier; wherein said sensing stepsinclude at least sensing different subsets of said unit cells atdifferent times.